A conventional approach to writing to a memory responds to each data change and each address change when writing to the memory array. Pulsed wordline approaches reduce current significantly when writing to and reading from memories. If the data is written to the memory array, and then either the address or the data changes states, new data is written. Each time the data or the address changes state, the new data is written to the memory array. For each data change, current is consumed to perform the write operation. Therefore, all data and address changes previous to the final data change consume unnecessary current. This causes the current consumption to be unpredictable during a write cycle.
Referring to FIG. 1, a circuit 10 is shown implementing a conventional pulsed wordline approach for writing to a memory. The circuit 10 generally comprises an address path block 12, a memory array block 14, a sense amplifier block 16, and output path block 18, a write driver block 20, a data transition detect block 22, an address transition detect block 24 and a control block 26. The address path block 12 and the address transition detect block 24 each receive a signal ADDRESS that is an externally generated address presented to the circuit 10. The address path block 12 presents a wordline signal WL to the memory array block 14. The memory array block 14 presents a signal TBUS to the sense amplifier block 16. The sense amplifier block 16 presents a signal SAOUT to the output path block 18. The output path block 18 presents a signal IO that may be presented to the external pins of the circuit 10. The signal IO is also presented to the write driver block 20 and the data transition detect block 22. The write driver block 20 presents data to the memory array block 14 and the sense amplifier block 16 receives data from the memory array block 14. The data transition detect block 22 presents a data transition detect signal DTD to the control block 26. The address transition detect block 24 presents an address transition detect signal ATD to the control block 26. The control block 26 also receives an external write enable signal WEB. The control block 26 also receives a signal WLDET from the memory array block 14. The control block 26 presents a signal WLEN to the address path block 12 and a signal SAEN to the sense amplifier block 16.
Referring to FIG. 2, a timing diagram illustrating the various signals of FIG. 1 is shown, where the signal WEB is equal to a "0". The signal ADDRESS has a transition 30. The signal ATD has a positive transition 32 that responds to the transition 30 of the signal ADDRESS. The signal WLEN has a positive transition 34 that responds to the negative transition 32 of the signal ATD. The signal WL has a positive transition 36 that responds to the positive transition 34 of the signal WLEN. The signal WLDET has a positive transition 38 that responds to the positive transition 36 of the signal WL. The signal TBUS has a transition 40 that responds to the positive transition 38 of the signal WLDET. The signal IO has a transition 42 and 44 that each indicate a change in the data has occurred.
The signal WLEN has a negative transition 48 that responds to the positive transition 38 of the signal WLDET. The signal WL has a negative transition 50 that responds to the negative transition 48 of the signal WLEN. The signal WLDET has a negative transition 52 that responds to the negative transition 50 of the signal WL. The signal TBUS has a transition 54 that responds to the negative transition 52 of the signal WLDET. The signal DTD has a positive transition 46 that responds to the transition 42 of the signal IO. The signal WLEN has a positive transition 56 that responds to the positive transition 46 of the signal DTD. The signal WL has a positive transition 58 that responds to the positive transition 56 of the signal WLEN. The signal WLDET has a positive transition 60 that responds to the positive transition 58 of the signal WL. The signal TBUS has a transition 62 that responds to the positive transition 60 of the signal WLDET. The signal WLEN has a negative transition 64 that responds to the positive transition 60 of the signal WLDET. The signal WL has a negative transition 66 that responds to the negative transition 64 of the signal WLEN. The signal WLDET has a negative transition 68 that responds to the negative transition 66 of the signal WL. The signal TBUS has a transition 70 that responds to the negative transition 68 of the signal WLDET.
The signal DTD has a positive transition 72 that responds to the transition 44 of the signal IO. The signal WLEN has a positive transition 74 that responds to the positive transition 72 of the signal DTD. The signal WL has a positive transition 76 that responds to the positive transition 74 of the signal WLEN. The signal WLDET has a positive transition 78 that responds to the positive transition 76 of the signal WL. The signal TBUS has a positive transition 80 that responds to the positive transition 78 of the signal WLDET. The signal WLEN has a negative transition 82 that responds to the positive transition 78 of the signal WLDET. The signal WL has a negative transition 84 that responds to the negative transition 82 of the signal WL. The signal WLDET has a negative transition 86 that responds to the negative transition 84 of the signal WL. The signal TBUS has a transition 88 that responds to the negative transition 86 of the signal WLDET.
The transition 44 indicates that stable data is ready to be written to the memory array block 14. Once a stable data transition 44 occurs, the transition 72-88 write the correct data to the memory array block 14. The signal ATD has a positive transition 32' that responds to a transition 30' of the signal ADDRESS. The transition 32' triggers the writing transitions 34'-54' that may or may not be valid transitions, depending on the state of the signal IO.